# ℹ️ Q & A Help Zone **URL:** https://community.aisler.net/c/help-zone/79.md?page=1 [Latest](https://community.aisler.net/latest.md) · [Categories](https://community.aisler.net/categories.md) · [Tags](https://community.aisler.net/tags.md) **Page:** 2 --- ## [How to assign multiple components in one footprint/symbol for assembly properly (KiCad 9)?](https://community.aisler.net/t/how-to-assign-multiple-components-in-one-footprint-symbol-for-assembly-properly-kicad-9/5472)
**Author:** [@oggimaster](https://community.aisler.net/u/oggimaster)\ **Replies:** 1\ **Last updated:** [December 17, 2025, 3:16pm UTC](https://community.aisler.net/t/how-to-assign-multiple-components-in-one-footprint-symbol-for-assembly-properly-kicad-9/5472 "2025-12-17T15:16:12Z")
Hello, I want to use some specific breakout boards with my pcb. The pinsockets have to be precisely placed, thats why I created one footprint for (for example) two seperate 1x8 pinsockets. I also created a splitted symb… --- ## [Small resistor tolerance and smart match](https://community.aisler.net/t/small-resistor-tolerance-and-smart-match/5468)
**Author:** [@Maligree](https://community.aisler.net/u/Maligree)\ **Replies:** 1\ **Last updated:** [December 9, 2025, 11:04am UTC](https://community.aisler.net/t/small-resistor-tolerance-and-smart-match/5468 "2025-12-09T11:04:54Z")
Hello everyone, just a short inquiry, the smart match is is limited to 50V rating for caps and 1W power for resistors. However, a tolerance of 0.5% for resistors is also not recognized for me. Am I doing something wrong… --- ## [Coplaner Waveguide Impedance testing](https://community.aisler.net/t/coplaner-waveguide-impedance-testing/5456)
**Author:** [@Ronak-Shah](https://community.aisler.net/u/Ronak-Shah)\ **Replies:** 3\ **Last updated:** [December 17, 2025, 12:53pm UTC](https://community.aisler.net/t/coplaner-waveguide-impedance-testing/5456 "2025-12-17T12:53:36Z")
Standard 4 layer PCB has only mentioned single ended , Diff 90 and 100 impedance Trace width and space requirements. This does not described Top or bottom Co-planer waveguide Trace width and Space from adjacent groun… --- ## [Rendering takes forever](https://community.aisler.net/t/rendering-takes-forever/5455)
**Author:** [@uwe](https://community.aisler.net/u/uwe)\ **Replies:** 1\ **Last updated:** [November 27, 2025, 2:49pm UTC](https://community.aisler.net/t/rendering-takes-forever/5455 "2025-11-27T14:49:31Z")
Hello, some 4-layer eagle design sts\_pogo\_11o allready produces before but now with small changes seems to run forever when rendering. I tried to abort ( Neu Starten), uploaded again and 20 minutes later it still rende… --- ## [A lot of information needed around Beautiful Boards+](https://community.aisler.net/t/a-lot-of-information-needed-around-beautiful-boards/5448)
**Author:** [@uwe](https://community.aisler.net/u/uwe)\ **Replies:** 6\ **Last updated:** [February 24, 2026, 1:58pm UTC](https://community.aisler.net/t/a-lot-of-information-needed-around-beautiful-boards/5448 "2026-02-24T13:58:46Z")
Hello, the announcement sounds great. However a lot of information around that is missing, e.g.: Layer material stackup, neede layout stckup, impedance info, rough price info, production time, etc Specifications are w… --- ## [How to add new part](https://community.aisler.net/t/how-to-add-new-part/5424)
**Author:** [@vj1](https://community.aisler.net/u/vj1)\ **Replies:** 1\ **Last updated:** [October 29, 2025, 5:37pm UTC](https://community.aisler.net/t/how-to-add-new-part/5424 "2025-10-29T17:37:58Z")
Hi, from time to time there is a missing part from the library and i need to add it. When doing so i take care of the PCB design rules, but i have no idea about the assembly rules. So, my question is: what are the imp… --- ## [Solder Mask Expansion Settings with Altium](https://community.aisler.net/t/solder-mask-expansion-settings-with-altium/5421)
**Author:** [@BRS-Motorsport](https://community.aisler.net/u/BRS-Motorsport)\ **Replies:** 1\ **Last updated:** [October 27, 2025, 11:12am UTC](https://community.aisler.net/t/solder-mask-expansion-settings-with-altium/5421 "2025-10-27T11:12:47Z")
Hello there, I’m currently working on a new PCB Layout, however when I uploaded it to Aisler every Pad which is connected to a Polygon is “bigger” / has less Soldermask around it: I used the given Soldermask Rules f… --- ## [XIAO on assembled board](https://community.aisler.net/t/xiao-on-assembled-board/5368)
**Author:** [@Davidmh](https://community.aisler.net/u/Davidmh)\ **Replies:** 1\ **Last updated:** [August 28, 2025, 5:25pm UTC](https://community.aisler.net/t/xiao-on-assembled-board/5368 "2025-08-28T17:25:51Z")
I want to have a PCB with a XIAO ESP32 built in. I grabbed the SMD footprint from the Seeed OPL library and made a quick prototype. It looks like this: (I did remove the inside pads so Aisler is happier). I pushed i… --- ## [PCB edge connector beveling?](https://community.aisler.net/t/pcb-edge-connector-beveling/5357)
**Author:** [@charles-wang-ctr-dot](https://community.aisler.net/u/charles-wang-ctr-dot)\ **Replies:** 1\ **Last updated:** [August 26, 2025, 9:01am UTC](https://community.aisler.net/t/pcb-edge-connector-beveling/5357 "2025-08-26T09:01:42Z")
Hello, Does AISLER offer PCB edge connector beveling such as detailed in this link? I am planning to design a PCB that fits in an M.2 slot which may require this feature. --- ## [Info for 4L stackup](https://community.aisler.net/t/info-for-4l-stackup/5343)
**Author:** [@David\_84](https://community.aisler.net/u/David_84)\ **Replies:** 1\ **Last updated:** [August 18, 2025, 12:03pm UTC](https://community.aisler.net/t/info-for-4l-stackup/5343 "2025-08-18T12:03:45Z")
Good day, im developing a new FC and i would like make it in a 4 layer stackup, but due some requirements i need an advice about the layers. Some sensors are shared on SPI bus, usart and pwm. Usually im working using S… --- ## [How to exclude a specific designator from assembly](https://community.aisler.net/t/how-to-exclude-a-specific-designator-from-assembly/5341)
**Author:** [@jiffaraka](https://community.aisler.net/u/jiffaraka)\ **Replies:** 4\ **Last updated:** [August 21, 2025, 11:38am UTC](https://community.aisler.net/t/how-to-exclude-a-specific-designator-from-assembly/5341 "2025-08-21T11:38:18Z")
In my design I have a 4.7uF capacitor that’s not populated, while two others are to be included. C45 is marked DNP in my KiCAD design, but I can’t seem to figure out how to exclude C45 while keeping C43 and C46 popula… --- ## [USA pricing and manufacturing](https://community.aisler.net/t/usa-pricing-and-manufacturing/5327)
**Author:** [@acedogblast](https://community.aisler.net/u/acedogblast)\ **Replies:** 3\ **Last updated:** [August 8, 2025, 3:54pm UTC](https://community.aisler.net/t/usa-pricing-and-manufacturing/5327 "2025-08-08T15:54:12Z")
Hello Aisler community, It would be helpful for customers in the USA to have updated pricing guide in USD. The current pricing structure is in Euros. After uploading my PCB gerbers, the quote I got was near double the e… --- ## [Received PCB with no filled zones](https://community.aisler.net/t/received-pcb-with-no-filled-zones/5265)
**Author:** [@Gabriel](https://community.aisler.net/u/Gabriel)\ **Replies:** 2\ **Last updated:** [July 10, 2025, 2:23pm UTC](https://community.aisler.net/t/received-pcb-with-no-filled-zones/5265 "2025-07-10T14:23:21Z")
Hello all, I am still new here so I believe am missing something very obvious. I created, ordered and received a simple PCB (RP PICO + an extra module), yet my idea was having filled ground zones on front/back areas. F… --- ## [0.5mm pitch BGA, Via just a tiny bit to large. Ideas needed](https://community.aisler.net/t/0-5mm-pitch-bga-via-just-a-tiny-bit-to-large-ideas-needed/5173)
**Author:** [@nilspipenbrinck-cons](https://community.aisler.net/u/nilspipenbrinck-cons)\ **Replies:** 2\ **Last updated:** [June 30, 2025, 10:29am UTC](https://community.aisler.net/t/0-5mm-pitch-bga-via-just-a-tiny-bit-to-large-ideas-needed/5173 "2025-06-30T10:29:20Z")
Hello, we are currently designing a couple of boards using a 0.5mm pitch BGA with a rather friendly landing pattern. It is a NXP MCXA144VMP with 64 pins on a 9x9 grid. The problem: Aisler’s minimum via size is just a ti… --- ## [Programming MCU](https://community.aisler.net/t/programming-mcu/4983)
**Author:** [@BillyBoy](https://community.aisler.net/u/BillyBoy)\ **Replies:** 1\ **Last updated:** [April 9, 2025, 4:31pm UTC](https://community.aisler.net/t/programming-mcu/4983 "2025-04-09T16:31:42Z")
Hi, I would like to get a small run of boards manufactured and assembled with Aisler. I need the MCUs (ATmega328p) to be programmed before delivery. I know I can get Digikey to pre-program MCUs and some assembly house… --- ## [Very expensive part price (WS2812B-2020)](https://community.aisler.net/t/very-expensive-part-price-ws2812b-2020/4943)
**Author:** [@DA68EEF3](https://community.aisler.net/u/DA68EEF3)\ **Replies:** 3\ **Last updated:** [April 2, 2025, 12:22pm UTC](https://community.aisler.net/t/very-expensive-part-price-ws2812b-2020/4943 "2025-04-02T12:22:53Z")
Hello there, my projects has 64 LEDs of type WS2812B-2020. When I search for the part the price is around 0,46€ in the search result. After assigning the part and updating to the latest price, the price increases to a… --- ## [Issue with self assembled MEMS BMP390 sensor](https://community.aisler.net/t/issue-with-self-assembled-mems-bmp390-sensor/4922)
**Author:** [@Neon](https://community.aisler.net/u/Neon)\ **Replies:** 1\ **Last updated:** [March 20, 2025, 11:19pm UTC](https://community.aisler.net/t/issue-with-self-assembled-mems-bmp390-sensor/4922 "2025-03-20T23:19:20Z")
Hi, I’m Leonardo Di Bartolomeo and i am part of the “La Sapienza” University of Rome Rocket Team, where we assemble small rocket models. We started developing our own boards this year and started a partnership with Ais… --- ## [Beautiful Boards on panel?](https://community.aisler.net/t/beautiful-boards-on-panel/4917)
**Author:** [@mm-utronix-se](https://community.aisler.net/u/mm-utronix-se)\ **Replies:** 1\ **Last updated:** [March 19, 2025, 12:20pm UTC](https://community.aisler.net/t/beautiful-boards-on-panel/4917 "2025-03-19T12:20:22Z")
I need my very small boards (16 x 38mm) on panels. Aisler use to deliver them on panels and that panels are OK. Is there a way to make sure I can get identical panels with every order? The reason is our assembly compa… --- ## [How to avoid Panel getting in the way of PCB cutout for Mid-Mount parts](https://community.aisler.net/t/how-to-avoid-panel-getting-in-the-way-of-pcb-cutout-for-mid-mount-parts/4902)
**Author:** [@traffael](https://community.aisler.net/u/traffael)\ **Replies:** 2\ **Last updated:** [June 2, 2025, 2:38pm UTC](https://community.aisler.net/t/how-to-avoid-panel-getting-in-the-way-of-pcb-cutout-for-mid-mount-parts/4902 "2025-06-02T14:38:25Z")
Hi Team! I recently ordered a PCB that had a mid-mount USB connector. The PCB was automatically manufactured with a panel (nice!), however that same panel was getting in the way of the mid-mount connector. How can I… --- ## [Design review request for a button PCB](https://community.aisler.net/t/design-review-request-for-a-button-pcb/4886)
**Author:** [@G\_us](https://community.aisler.net/u/G_us)\ **Replies:** 5\ **Last updated:** [March 19, 2025, 1:29pm UTC](https://community.aisler.net/t/design-review-request-for-a-button-pcb/4886 "2025-03-19T13:29:43Z")
Hello! I’m trying to design and manufacture a PCB for the first time. I want to have 5 buttons and a rotary encoder on the “front” of the PCB and a 16 pin header on the bottom. I have designed this PCB for it but I ha… --- ## [4 layers PCB stackup](https://community.aisler.net/t/4-layers-pcb-stackup/4866)
**Author:** [@Tynnor](https://community.aisler.net/u/Tynnor)\ **Replies:** 1\ **Last updated:** [September 29, 2026, 1:17pm UTC](https://community.aisler.net/t/4-layers-pcb-stackup/4866 "2026-09-29T13:17:18Z")
Hello, I am working on a 4 layers PCB board with some controlled impedance tracks. I have a doubt on the stackup I should use because I don’t see the same things on the stackup picture on the page below and the prepeg… --- ## [Quasi castellated pads to achieve partial board edge metallization?](https://community.aisler.net/t/quasi-castellated-pads-to-achieve-partial-board-edge-metallization/4856)
**Author:** [@datenwolf](https://community.aisler.net/u/datenwolf)\ **Replies:** 2\ **Last updated:** [April 24, 2025, 9:38am UTC](https://community.aisler.net/t/quasi-castellated-pads-to-achieve-partial-board-edge-metallization/4856 "2025-04-24T09:38:55Z")
I was wondering if one could use the rules for generating castellated edges to achieve partial metallization of a boards edges. Specifically I’m interested in mounting edge-launched SMA connected inset into the board, ma… --- ## [Notes of Product No. on Your PCB](https://community.aisler.net/t/notes-of-product-no-on-your-pcb/4768)
**Author:** [@TomasApo](https://community.aisler.net/u/TomasApo)\ **Replies:** 1\ **Last updated:** [April 17, 2025, 5:58pm UTC](https://community.aisler.net/t/notes-of-product-no-on-your-pcb/4768 "2025-04-17T17:58:50Z")
Hi, Does Aisler offer the posibility of numbering the PCBs at a desired location? E.G --- ## [Help with Plated Slots for Würth USB-C Port in Fusion 360](https://community.aisler.net/t/help-with-plated-slots-for-wurth-usb-c-port-in-fusion-360/4734)
**Author:** [@Alexander96](https://community.aisler.net/u/Alexander96)\ **Replies:** 5\ **Last updated:** [February 3, 2025, 4:51pm UTC](https://community.aisler.net/t/help-with-plated-slots-for-wurth-usb-c-port-in-fusion-360/4734 "2025-02-03T16:51:40Z")
Hello Aisler Community, I’m designing a PCB in Fusion 360 and using a Würth USB-C port (629722000214). However, I’m struggling to correctly implement the plated slots (elongated holes) for the mounting pads, as the mill… --- ## [How do you drill holes? Or: Which drills you use?](https://community.aisler.net/t/how-do-you-drill-holes-or-which-drills-you-use/4659)
**Author:** [@i440bx](https://community.aisler.net/u/i440bx)\ **Replies:** 2\ **Last updated:** [January 10, 2025, 4:07pm UTC](https://community.aisler.net/t/how-do-you-drill-holes-or-which-drills-you-use/4659 "2025-01-10T16:07:31Z")
Hi Aisler Team, I would like to standardize my footprint library and have seen that I have many holes for pads in the sizes 0.7mm to 0.9mm. After the last order I went to my stock with an empty PCB and realized that fo… --- ## [2 layer](https://community.aisler.net/t/2-layer/4568)
**Author:** [@projects-nbahn-at](https://community.aisler.net/u/projects-nbahn-at)\ **Replies:** 1\ **Last updated:** [January 3, 2025, 7:57pm UTC](https://community.aisler.net/t/2-layer/4568 "2025-01-03T19:57:42Z")
By default, a board is labeled with layer 25 (tName). I would also like to have layer 27 (tValue) printed on the board. What do I have to do when ordering? --- ## [Plated Edges - How to design?](https://community.aisler.net/t/plated-edges-how-to-design/4553)
**Author:** [@Alphaprot](https://community.aisler.net/u/Alphaprot)\ **Replies:** 14\ **Last updated:** [February 6, 2025, 7:10pm UTC](https://community.aisler.net/t/plated-edges-how-to-design/4553 "2025-02-06T19:10:13Z")
Good day, In order to reduce the ESD risk on a capacitive touch sensing board, I would like to implement edge plating on the design in order to surround the edges on all four sides. I am aware that a fully plated edge … --- ## [RF designs with aisler.net: FR4 parameters needed](https://community.aisler.net/t/rf-designs-with-aisler-net-fr4-parameters-needed/4532)
**Author:** [@thomas-grande-gmx-de](https://community.aisler.net/u/thomas-grande-gmx-de)\ **Replies:** 3\ **Last updated:** [December 5, 2024, 11:44am UTC](https://community.aisler.net/t/rf-designs-with-aisler-net-fr4-parameters-needed/4532 "2024-12-05T11:44:54Z")
Dear aisler team, I am designing mostly pcbs from 30 to 915MHz. For integration of pcb inductivities and capacitiesI would like to know the characteristic material values of your FR4 materials (2 Layer, 1.6mm thickness… --- ## [Individuelle Form der Leiterplatte](https://community.aisler.net/t/individuelle-form-der-leiterplatte/4495)
**Author:** [@Vogt](https://community.aisler.net/u/Vogt)\ **Replies:** 2\ **Last updated:** [November 22, 2024, 3:47pm UTC](https://community.aisler.net/t/individuelle-form-der-leiterplatte/4495 "2024-11-22T15:47:38Z")
Kann ich der Leiterplatte eine eigene Form geben oder ist diese an eine quadrtische gebunden? Ich nutz KiCad 8. --- ## [BGA support](https://community.aisler.net/t/bga-support/4481)
**Author:** [@David\_84](https://community.aisler.net/u/David_84)\ **Replies:** 7\ **Last updated:** [November 26, 2024, 8:53pm UTC](https://community.aisler.net/t/bga-support/4481 "2024-11-26T20:53:11Z")
Good day, as im developing an FC based on STM32h743 package UFBGA or TFBGA , i need info a about the vias supported size for the funout in a 4 layer board as 6 layer it not avaiable for now. Regards [Previous page](https://community.aisler.net/c/help-zone/79.md) [Next page](https://community.aisler.net/c/help-zone/79.md?page=2)