The BQ27220YZFR is a BGA package with a fine-pitch of 0.5 mm between solder balls. According to the 4 Layer 35µm ENIG design rules, the minimum spacing between copper is 125 µm, with a minimum track width of also 125 µm. With that, it doesn’t seem possible to route the IC in accordance with the design rules.
I’m afraid that’s going to be difficult. What minimum spacing and/or track would you need to route to the GND pad? Generally, for assembly projects, you have the option to send us a custom request via our contact form. Often, a solution can be found by manufacturing the PCBs in a special/custom production run. Alternatively, you could consider capped vias here. However, these are also non-standard and would need to be requested individually.
I assume there is no option to use a larger part with lower requirements?
thanks for the reply. Comparing a few manufacturers, I think the most feasible way of routing out the 0.5 mm BGA is with via-in-pad. A via with a 0.2 mm hole, and 0.35 mm diameter. Placing that in the middle of the pad gives 0.2 mm spacing between the copper of the pad and the via. This seems to be, at a slightly higher price, possible by some manufacturers.
My testing revealed that routing out would require 0.09 mm / 3 mil tracks with 0.051 mm / 2 mil spacing of the track to the SMD pad (when not making the pad size any smaller; however, the pad size is already at the minimum specified by Ti).
When changing the pad size to 0.2 mm (down from 0.25 mm), I can route out with a 0.1 mm track, and 0.1 mm spacing between track & pad.
I agree, it would be better to use a different part. I’ll get back to the drawing board, I could probably get away without a BMS IC in the first place.