# PCB Design Rules **URL:** \ **Category:** 🔎 Design Rules\ **Created:** [December 17, 2021, 11:04am UTC](https://community.aisler.net/t/pcb-design-rules/41 "2021-12-17T11:04:09Z")\ **Posts on this page:** 2\ **Page:** 1
**Author:** ![Thea](https://community-cdn.aisler.net/user_avatar/community.aisler.net/thea/32/1177_2.png) [@Thea](https://community.aisler.net/u/Thea)\ **Post date:** [December 17, 2021, 11:04am UTC](https://community.aisler.net/t/pcb-design-rules/41/1 "2021-12-17T11:04:09Z")
# Board surface finishes We offer 2 Layer PCBs with an option of HASL and ENIG as surface finish, if you use small drills, castellated edges or small trace width/spacing it is required to choose ENIG as surface finish. | Feature | HASL allowed | ENIG required | | --- | --- | --- | | min. drill diameter | ≥ 0.3 mm | ≥ 0.25 mm | | contains castellated holes | ✖ | ✔ | | min. trace width/spacing (Cu 35 µm) | 200 µm/150 µm | 125 µm/125 µm (100 µm /100 µm for 6L+) | | min. trace width/spacing (Cu 70 µm) | 225 µm/225 µm | 175 µm/175 µm | # Design Rules We have different rules depending on the technologies used. ## 35 µm - [2L 35 µm HASL](https://community.aisler.net/t/2-layer-1-6-mm-35-m-hasl-design-rules/3735) - [2L 35 µm ENIG](https://community.aisler.net/t/2-layer-1-6mm-35-m-enig-design-rules/3732) - [4L 35 µm ENIG](https://community.aisler.net/t/4-layer-35-m-enig-design-rules/3733) - [6L+ 35 µm ENIG](https://community.aisler.net/t/6+-layer-35-m-enig-design-rules/5467) ## 70 µm - [2L 70 µm HASL](https://community.aisler.net/t/2-layer-1-6mm-70-m-hasl-design-rules/5464) - [2L 70 µm ENIG](https://community.aisler.net/t/2-layer-1-6mm-70-m-enig-design-rules/5465) ---
**Author:** ![Thea](https://community-cdn.aisler.net/user_avatar/community.aisler.net/thea/32/1177_2.png) [@Thea](https://community.aisler.net/u/Thea)\ **Post date:** [September 25, 2024, 8:57am UTC](https://community.aisler.net/t/pcb-design-rules/41/40 "2024-09-25T08:57:34Z")