# Quasi castellated pads to achieve partial board edge metallization?

**URL:** <https://community.aisler.net/t/quasi-castellated-pads-to-achieve-partial-board-edge-metallization/4856>\
**Category:** ℹ️ Q & A Help Zone\
**Tags:** beautiful-boards, pcb-design\
**Created:** [March 3, 2025, 2:27pm UTC](https://community.aisler.net/t/quasi-castellated-pads-to-achieve-partial-board-edge-metallization/4856 "2025-03-03T14:27:07Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![datenwolf](https://community-cdn.aisler.net/letter_avatar_proxy/v4/letter/d/a5b964/32.png) [@datenwolf](https://community.aisler.net/u/datenwolf)\
**Post date:** [March 3, 2025, 2:27pm UTC](https://community.aisler.net/t/quasi-castellated-pads-to-achieve-partial-board-edge-metallization/4856/1 "2025-03-03T14:27:07Z")

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I was wondering if one could use the rules for generating castellated edges to achieve partial metallization of a boards edges. Specifically I’m interested in mounting edge-launched SMA connected inset into the board, making the solder flow into the gap between the connector and the board.

Following the rules laid out in [Castellated edges](https://community.aisler.net/t/castellated-edges/48) I came up with something in KiCad that renders in the KiCad 3D viewer as following:

 ![metallization](https://community-cdn.aisler.net/uploads/default/original/2X/6/69199f21840fff594b80a6ad00a5b6b5a9bb2477.jpeg)

In the Aisler PCB viewer the board is processed without reporting warnings or errors and rendered as

 ![2025-03-03_15-24](https://community-cdn.aisler.net/uploads/default/original/2X/b/b276df43311a1360edf8ebba14a72b76b6561299.png)

But I wonder if this can actually be manufactured without problems. How viable is this?

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**Author:** ![Thea](https://community-cdn.aisler.net/user_avatar/community.aisler.net/thea/32/1177_2.png) [@Thea](https://community.aisler.net/u/Thea)\
**Post date:** [March 14, 2025, 11:56am UTC](https://community.aisler.net/t/quasi-castellated-pads-to-achieve-partial-board-edge-metallization/4856/2 "2025-03-14T11:56:23Z")

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Hi @datenwolf ,

Some Members of your community did something similar successfully already.  
(Back then on our 6 Layer Pool, which we discontinued since) but from a mechanical manufacturing standpoint It’s still the same.

 ![edge_metal](https://community.aisler.net/uploads/default/original/1X/3a9cf7ed3dfbda739b05803e22730db5e5e26440.jpeg)

But please note that this method is still a bit “hacky” and there may be some copper burrs you have to clean off manually.

You can find their example board in this Gitub repository.

> **[GitHub - toammann/Multilayer\_SMA2Microstrip: Development of an SMA coaxial to microstrip...](https://github.com/toammann/Multilayer_SMA2Microstrip?tab=readme-ov-file)**
>
> Development of an SMA coaxial to microstrip transition using open source software (openEMS)

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**Author:** ![datenwolf](https://community-cdn.aisler.net/letter_avatar_proxy/v4/letter/d/a5b964/32.png) [@datenwolf](https://community.aisler.net/u/datenwolf)\
**Post date:** [April 24, 2025, 9:38am UTC](https://community.aisler.net/t/quasi-castellated-pads-to-achieve-partial-board-edge-metallization/4856/3 "2025-04-24T09:38:55Z")

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Just a quick followup on the project: Using the SMA edge launch footprint I created I ordered a board at Aisler. This is the result:

 ![IMG_20250422_121018](https://community.aisler.net/uploads/default/original/2X/f/fa5a16cebd0be6939e1ae3c482fa012097bc9da0.jpeg)

_It came out beautiful!_

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**Author:** ![system](https://community-cdn.aisler.net/user_avatar/community.aisler.net/system/32/28_2.png) [@system](https://community.aisler.net/u/system)\
**Post date:** [October 15, 2026, 1:34pm UTC](https://community.aisler.net/t/quasi-castellated-pads-to-achieve-partial-board-edge-metallization/4856/4 "2026-10-15T13:34:23Z")

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