Hi,
any chance to get an alternative 4 layer stackup? The 245 Āµm trace width for 50 Ohm is a little limiting. With e.g. a 0.12 mm prepreg it could be reduced to ~185 Āµmā¦
Cheers,
Johann
You can contact our support regarding alternative stackups for volume production.
We only offer the current stackup, this way we are able to offer better prices and turnaround time for everyone. Would your design allow for a grounded coplanar waveguide? This could help getting the tracewidth smaller.
Thanks for the fast response!
I want to route out the gpios of an raspberry pi compute module 4 with 50 Ohm. With the cm4 connector having a two row 0.4 mm pitch, this is basically impossible with 245 Ī¼m tracks. And the 138 Ī¼m prepreg also suggests a quite large 280 Ī¼m track clearanceā¦
I do understand that offering only 1 stackup is most cost effective. Do you maybe have any plans to change the existing one? Or am I the only one asking??
Iām just an hobbyist, so no mass production plannedā¦ 
We currently do not plan to change it.
May I ask why you want to use 50 Ohm traces for the GPIOs? The CMOS output stages are to my knowledge not impedance matched. The idea of controlled imedance is to reduce signal reflection 50Ohm was just chosen as a value that is easily manufacturable. Something slightly lower or higher will not be an issue for just GPIOs. Other factors like good decoupling or return paths are more important. The thight pinout of the CM4 connector is quite the edgecase.
50 Ohms is not an absolute must, basically something which I use by default as itās ānever wrongā. The necessary clearance of 2H for appropriate crosstalk reduction bothers me more. I have too many parts (DSI connector, CSI connector, RTC, Fan controller, USB hub and more) to place, so that I cannot afford the track clearance, even when routing on top and bottom. Also the 90 and 100 Ohm differential pairs (which are mandatory) seem difficult for what I want to pack onto a 10x10 cm board. Your process seems to allow 125 Āµm width and clearance, but the prepreg thickness doesnāt seem to allow me to use it for this particular project.
Iām still glad that I was pointed to aisler. Your support (responses this fast late evening, wow!) is convincing and I like the no frills approach. For further projects Iām sure I will check again!
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I am aware of the shortcomings when it comes to high density designs with our stackup.
Would using 6 Layers be an option to you? This could give you more room for the traces.
I appreciate your feedback and I will bring it up when we decide to expand our portfolio.
6 layers are an interesting idea. I thought a little about it, but I guess it will not work out for me:
- I would consider my knowledge not sufficient to actually use it; I like 4 layers with the two inner layers being ground as this seems to be the easiest for me: The reference plane for proper return signals is ājust thereā (you only need to avoid routing over voidsā¦), and both top and bottom layer can be equally used once you have defined your impedance settings.
- Iām not sure if it would be sufficient - in areas with many vias, I wonāt be able to route singals in the inner layers
Additionally I identified other constraints in your HD boards which will not work for me:
- Minimal via seems to be 0.2/0.6, but I already use 0.2/0.5 (and I think I canāt route out the RPi cm4 connectors with 0.6 vias)
- I have copper even on the board edge
Iām attaching a screen shot of how Iāve done the boards. Vias are 0.5 and traces are 0.185 with a clearance of 0.240. I guess you are simply not targeting this kind of boards at the moment. Maybe in the futureā¦ 
