I loaded your KiCad template from gitub which specifies minimum annular width to be 0.2mm. So a typical through hole TDK 0.1uF capacitor fails, because TDK’s footprint has 0.175mm. However, your blog page says the minumum anilar ring to be 300μm (0.3mm). In fact, there are numerous pages scattered all over your blog site, but I lack the enthusiasm to read them all.
So my question is - which should I believe, or am I mixing up the naming conventions?
As you can see in the github issues, I also see discrepancies between the github design rules and the rules from the webpage
We will update the rules on GitHub soon.
Regarding the annular ring, there’s no difference for KiCad between the Via annular ring and PTH annular ring. So you can only enter one value and may need to use a custom rule.
We chose 0.3mm as the new value as we enlarged PTH drills as described here: Plated and Non-Plated Holes if a too small is chosen initially, the end annular ring is not large enough for good solderability.
@anon6029747 Can you link us the footprint you mean?