Hi @vinzc
Thank you for your message!
I just opened the footprint in KiCad. As far as I can see, the pad dimensions are 1.05 mm × 1.5 mm, while the hole has a diameter of 0.75 mm. This results in a minimum annular ring of (1.05 mm − 0.75 mm) / 2 = 0.15 mm (150 µm).
According to the currently published design rules for 2-layer 35 µm HASL, which corresponds to “simple”, the minimum annular ring for component through-holes is actually 300 µm, and not 200 µm. See also here.
It looks to me like KiCad does not differentiate between annular rings for vias and those for component through-holes in its DRC configuration, and my colleague who set up the DRC files obviously chose the lower limit.
Due to the rather narrow spacing between the pads, there is unfortunately not much room for modifying the pad dimensions. The current clearance between the pad edges is just 220 µm. So even when enlarging the pads up to a clearance of 150 µm (minimum copper spacing), we can only increase the annular ring by 35 µm per pad, resulting in an annular ring of 185 µm.
I would not recommend reducing the hole diameter, as this may complicate the assembly—or even make it impossible if the final hole diameter is too small for the component pins.
Using our complex design rules and an ENIG surface finish does not solve the issue either. The minimum copper spacing is reduced to 125 µm, allowing you to increase the pad width to 1.145 mm. This results in an annular ring of nearly 200 µm, which is still below the required 300 µm.
Although we are below the specified requirement in some respects, the through-hole plating itself should still be properly manufactured. The pad ring is very thin in some areas, but since the pads are oval-shaped, it should still be possible to solder the component. Nevertheless, this is of course not ideal.
I assume using another footprint is not an option? 
Kind regards,
Manuel