I am designing a 4-layer capacitive trackpad based on Azoteq’s AZD068 recommendations.
The intended stack-up is:
- F.Cu: sensing electrodes
- In1.Cu: intentionally no copper beneath the sensing area
- In2.Cu: ground plane
- B.Cu: components and routing
The absence of copper on In1.Cu is intentional, because copper directly behind the sensing electrodes would increase capacitive loading.
Could you please confirm the following?
- Is it acceptable for In1.Cu to be completely empty, or at least empty over a large part of the PCB?
- Will plated through-vias still have a continuous barrel through the empty In1.Cu layer?
- Will AISLER preserve the empty layer exactly as submitted? Is it worth adding at least a route along the layer contour?
- Are there any concerns regarding warpage, lamination quality, or manufacturability due to the strongly unbalanced copper distribution?
The board is intentionally designed this way for capacitive-sensing performance, so adding a copper fill on In1.Cu would not be desirable.