Verify KiCad edge clearance on upload

Aisler supporting KiCad board files are very nice for the consumer. It can however give problems when saving without refilling. When refilling doesn鈥檛 happen it will result in a edge to copper clearance of 0.

Same problem, someone else: Re-fill zones on Save (#14747) 路 Issues 路 KiCad / KiCad Source Code / kicad 路 GitLab

Check or visualise edge clearance on upload.

Possible solution:
KiCad has a command line interface that can be used to export layers to SVG. Exporting all copper layers, thickening the edge line to 2x 0.3mm and masking that on top of copper layers will expose the offending parts per layer.

Step 1:
kicad-cli.exe pcb export svg -l Edge.Cuts,F.Cu --exclude-drawing-sheet '.\my-project.kicad_pcb'

Step 2:
Find and replace the edge line thickness, change to 0.6mm (SVG is just XML)

Step 3:
Use an SVG tool (Like Inkscape) to mask Copper layers with the thickened edge. You could use a client-side library like SVG.js v3.0 | Other Elements.

Step 4:
Compare resulting layer with a blank canvas: blank canvas means no edge violations. If errors are found the SVG can be shown to the uploader.