4 Layer HD Design Rules

4 Layer HD Design Rules

Last Updated: 28/02/2024
Imperial measures are rounded from metric measurements.

Design Rule Files

You want to start right away? We provide design rule files for Eagle, KiCad and DipTrace on Github .

PCB Dimension

We accept PCBs within these dimensions for our prototype service, contact our support if your design does not meet these criteria.

min board size min. dimension >10 mm / >0.4 in
max pcb size max. size 400 x 400 mm / 15.74 in x 15.74

Surface Finish

We use Electroless Nickel Immersion Gold (ENIG) as surface finish for our 4 Layer HD PCBs, this surface finish offers good surface planarity and high oxidation resistance.
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ENIG surface finish ENIG
Surface Finish ENIG gold thickness 0,05 µm -0,1 µm

Minimum Copper Features

Description Capability
min. tracewidth min. tracewidth 125 µm / 5 mil
min.  SMD pad size min. SMD pad size 200 µm / 8 mil

Minimum Copper Spacing / Clearance

min. copper spacing min. spacing copper / copper 125 µm / 5 mil
min. spacing NPTH copper) min. spacing NPTH / copper 250 μm / 10 mil
min. spacing NPTH Slot copper min. spacing NPTH slot <1.8 mm / copper 300 μm / 12 mil
min. spacing 1.8 mm Slot _ copper min. spacing NPTH slot >= 1.8 mm / copper 300 μm / 12 mil
Edge clerance min. copper to edge clearance 300 μm / 12 mil

Plated Through Hole (PTH)

min. PTH drill min. PTH drill size 0.5 mm / 0.02 in
max. PTH drill max. PTH drill size 5.6 mm / 0.22 in
min. annular ring PTH min. PTH annular ring 300 μm / 12 mil

Vias

min.  via drill min. via drill 0.1 mm / 4 mil
max. via drill max. via drill 0.5 mm / 20 mil
min. annular ring via min. via annular ring 200 μm / 8 mil

Non Plated Through Hole (NPTH)

min. NPTH drill 0.5 mm / 20mil
max. NPTH drill 5.6 mm / 0.22 in

Minimum Drill Spacing

min. drill spacing ) min. drill spacing 300 μm / 12 mil

NPTH Slots

preferred slot diameter preferred NPTH slot diameter >= 1.8 mm / 0.07 in
min. NPTH slot diamater min. NPTH slot diameter 0.8 mm / 0.032 in
max. NPTH slot diamater max. NPTH slot diameter :infinity: No restriction

PTH Slots

min. PTH slot diamater min. PTH slot diameter 0.7 mm / 0.028 in
max. PTH slot diamater max. PTH slot diameter 2.6 mm / 0.11 in
min. PTH slot annular ring min. PTH slot annular ring 300 µm / 12 mil

Silkscreen

We use Peters SD2692 ink for the silkscreen on our PCBs and apply it using the direct printing method. The smallest supported width is 150 µm / 6 mil, all silkscreen features with a width less of that will be adjusted. Silkscreen printed on pads is not supported, we use openings in the soldermask as reference to cut away / remove the silkscreen in the affected area. Do not use the silkscreen to produce large fillings, designs which cover more than 25% per PCB side will be rejected.

min. silkscreen text height min. silkscreen text height 800µm / 32 mil
min. spacing silkscreen / pad min. spacing silkscreen / pad 125 µm / 5 mil
silkscreen on pad silkscreen on pad not supported
Silkscreen edge clearance min. spacing silkscreen / edge 400 µm / 16 mil
Large Silscreen fillings max. Silkscreen 25% of Board size

Soldermask

We use high-quality Peters Elpemer AS 2467 SM-DG green soldermask which is well suited for the ENIG finish. Please refer to our soldermask specification for the electrical properties of the soldermask.

min. soldermask dam min. soldermask dam 75 µm / 3 mil

Castellated Edges

We offer castellated edges in our 4 Layer HD pool free of charge, please refer to our documentation on how you can set them up.

castellated-edges-enig castellated edges Supported

Stackup

We use Panasonic Prepreg 1080 Type R-1551(W) (58.9 KB), Peters coatings and Elga Copper foil.

Our Boards are RoHS and REACH compliant.

The following track layouts can be used to realize defined impedance. Please note that these values only provide a basic orientation. Interference factors such as angles, meanders or vias in the routing of the tracks may negatively affect the intended impedance.

Defined Impedance

Type Impedance Signal- / Reference Layer width space width
Single Ended 50 Ω TOP / IN1, BOT / IN2 245 µm - -
Differential pairs 90 Ω TOP / IN1, BOT / IN2 230 µm 165 µm 230 µm
Differential pairs 100 Ω TOP / IN1, BOT / IN2 190 µm 180 µm 190 µm

Additional Notes

  • Buried, blind, micro or tented vias are not supported
  • User-defined subpanels are not allowed, see also here