Hello,
the eagle DRC files at aisler-support/eagle/drc at master · AislerHQ/aisler-support · GitHub do not match the technical capabilities given on the Website,
E.g. aisler_e_layer_simple give minimum spacing of 0.175 mm, minimum width of 0.2 mm and minimum drill 0.45 mm. PCB Design Rules tells 0.15/0.2/0.3.
Manufacturer DRC files should match the capabilities.
Those are indeed outdated I will update them soon.
These still seem outdated btw
There were a few changes in the past weeks, for example minimum via drill size for HD changed a lot. I don’t think any of those changes were ported to Github.
At least for KiCad I can confirm that these rules are as well outdated.
Ive now updated all DRC files on Github.