Plated Edges - How to design?

Good day,

In order to reduce the ESD risk on a capacitive touch sensing board, I would like to implement edge plating on the design in order to surround the edges on all four sides.

I am aware that a fully plated edge around the whole rectangular PCB-perimeter is not possible due to the bridges/tabs that connect the PCB to your frame.

Thea wrote in mid-2023, that edge plating was supported.

What copper clearances around the board edge do I need to apply that you know what planes shall be connected to the plated edge and which not/be pulled back?

Is there anything else I need to keep in mind in order to prototype this on your 4-Layer-ENIG pool?

Looking forward to hearing from you.
Best regards,
Yannik

To provide help, I would need to know which PCB design tool you are using.

Hey Thea,
Thank you for looking further into this. The EDA tool I am using is KiCAD (v8).

Before you ask, the layout work itself has not started yet, since I wanted to ask for clarification and possible caveats first.

Best regards,
Yannik

I thought it might be helpful to provide some further information of the current state.

Currently, I pulled all areas which shall not be connected to the plated edge/side back by at least 300 micron specified in the 1.6 mm 4 Layer ENIG design rules.
Layers which shall get connected to the side plating extend fully to the board outline.

The solder mask expands fully to the board outline as of now.

I also specified custom bridges so that the side plating gets disrupted by the NPT-mousebites only in known places.

Looking forward for your directions.

All the best for 2025 :slight_smile: :confetti_ball:

In case you and your engineers need the project files of the finalized PC, they can be found by the project ID BLCWKJIJ

Best regards,
Yannik

Hi Yannik :wave:

I hope you had a good start to the new year. :slight_smile:

We mill the PCB outlines after the plating during the manufacturing, so you need to place plated slots in your design and then run the board outline through the plated slot. A wider width of 1.8mm will make the plated slot easier to manufacture.

An example of how it’s implemented can be seen here:


Hey Thea,

thank you very much for your helpful answer and for linking a reference design. :blush:

I tried setting my board up with PTH slots (300 µm annular, 1.8 mm slot width) like you suggested:

I am afraid though that the extensive use of slots to achieve all around plating would lead to a non-producible design. Most of the board outline would be milled away at an early manufacturing stage.

Do I need to interrupt the plated edges more frequently for it to work?

As of now, the design triggers a “critical use of elongated holes” warning and requires contacting support, though the slot width is 1.8 mm (no need for nibbling, in accordance with Plated and Non-Plated Slots).

Best regards,
Yannik

A follow-up question I forgot to ask:

How wide do the custom bridges need to be? In the post above, I spec’ed them at 4 mm, but wonder if you got a default value for the bridge width.

Regarding my thoughts on manufacturability - would it work better with more bridges like so (just a quick mockup on the Edge.Cuts layer):

Best regards,
Yannik

Edit: I missed that PTH slots are nibbled no matter what width is used:

4mm should work, I spoke with the production folks again, they wanted to clarify that the process is not recommended for large quantities of boards, so we will manufacture a few dozens using this process but not hundreds. If you require more boards, we will use have to use a different approach.

Hey Thea,
just to keep the topic updated:
I submitted a support ticket, so that someone can look over the proposed design and eventually (hopefully :smile: ) clear it for manufacturing, as it requires manual clearance because the total PTH slot length is above the granted 75 mm.

I will provide a picture of the boards if they arive so that this thread may be somewhat used as a future reference.

If it turns out to be functional, I might post in the “Made with AISLER”-section as well; we will see… :blush:

Best regards,
Yannik