Quasi castellated pads to achieve partial board edge metallization?

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1

I was wondering if one could use the rules for generating castellated edges to achieve partial metallization of a boards edges. Specifically I’m interested in mounting edge-launched SMA connected inset into the board, making the solder flow into the gap between the connector and the board.

Following the rules laid out in Castellated edges I came up with something in KiCad that renders in the KiCad 3D viewer as following:

metallization
metallization3639×2021 302 KB

In the Aisler PCB viewer the board is processed without reporting warnings or errors and rendered as

2025-03-03_15-24
2025-03-03_15-242185×1888 55.1 KB

But I wonder if this can actually be manufactured without problems. How viable is this?

2

Hi @datenwolf ,

Some Members of your community did something similar successfully already.
(Back then on our 6 Layer Pool, which we discontinued since) but from a mechanical manufacturing standpoint It’s still the same.

edge_metal
edge_metal1744×1076 103 KB

But please note that this method is still a bit “hacky” and there may be some copper burrs you have to clean off manually.

You can find their example board in this Gitub repository.